1. Field of the Invention
The present invention relates to a solid-state image pickup apparatus using a CCD image sensor, and more particularly to an improvement of output characteristics in an output section of such an image sensor.
2. Description of the Related Art
For solid-state image pickup, such as used in TV cameras equipped with a CCD image sensor, scanning timing is set based on synchronization signals in accordance with a predetermined television format. For example, in the NTSC format, the vertical scanning period is set to 1/60 second and the horizontal scanning period is set to 2/525 of the vertical scanning period. The result is that the picture information for a single image plane is output in the form of successive picture signals, one horizontal line at a time.
FIG. 1 is a block diagram showing the basic structure of an image pickup apparatus that uses a CCD image sensor, while FIGS. 2 and 3 are timing charts illustrating the operations thereof.
A typical frame transfer type CCD image sensor 1 comprises an image pickup portion 1i, a storage portion 1s, a horizontal transfer section 1h, and an output section 1d. The image pickup portion 1i comprises a plurality of parallelly arranged CCD shift registers, where a plurality of bits follow in succession in the vertical direction. Respective bits of these shift registers form optical pixels and accumulate information charges, which are generated by input light during an image pickup period. The storage portion 1s comprises a plurality of CCD shift registers, which are arranged in succession to the respective shift registers of the image pickup portion 1i, and wherein the number of bits corresponds to the respective shift registers. The bits of these shift registers temporarily store respective information charges that are transferred out from the pixels of the image pickup portion 1i. The horizontal transfer section 1h comprises a single CCD shift register, the bits of which are connected to the outputs of the shift registers of the storage portion 1s. The information charges, which are transferred one horizontal line at a time from the storage portion 1s, are transferred in sequence to the output section 1d. The output section 1d comprises a capacitance for receiving information charges and is provided at the output side of the horizontal transfer section 1h. The output section 1d, the capacitance of which receives information charges that are transferred out from the horizontal transfer section 1h, outputs voltage values proportional to the charge amounts. Changes in the voltage values that are output become an image signal Y0(t).
A drive circuit 2 comprises a frame clock generator portion 2f, a vertical clock generator portion 2v, a horizontal clock generator portion 2h, a reset clock generator portion 2r, and a sampling clock generator portion 2s. The frame clock generator portion 2f generates in response to a frame shift timing signal FT a frame clock xcfx86f for supply to the image pickup portion 1i. The information charges that have accumulated in the pixels of the image pickup portion 1i are transferred at a high speed to the storage portion 1s each vertical scanning period. The vertical clock generator portion 2v generates a vertical clock xcfx86v for the storage portion 1s in response to a vertical synchronization signal VT and a horizontal synchronization signal HT. As a result, as the information charges that are transferred out from the image pickup portion 1i are captured and temporarily stored, and the stored information charges are then transferred one horizontal line at a time to the horizontal transfer section 1h during each horizontal scanning period. The horizontal clock generator portion 2h generates in response to the horizontal synchronization signal HT a horizontal transfer clock xcfx86h for supply to the horizontal transfer section 1h. As a result, the information charges that were captured one horizontal line at a time in the horizontal transfer section 1h from the storage portion 1s are transferred in sequence to the output section 1d. The reset clock generator portion 2r generates, in synchronization with the operation of the horizontal clock generator portion 2h, a reset clock xcfx86r for supply to the output section 1d for discharging the information charges that are stored in the capacitance of the output section 1d. As a result, the information charges that are output from the horizontal transfer section 1h to the output section 1d are stored in the capacitance of the output section 1d in one pixel units. The sampling clock generator portion 2s, similar to the reset clock generator portion 2r, then generates a sampling clock xcfx86s for supply to a sample-and-hold circuit 4 in synchronization with the operation of the horizontal clock generator portion 2h for sequentially sampling the image signal Y0(t).
A timing control circuit 3 operates based on a reference clock CLK having a fixed period, and generates the vertical synchronization signal VT and horizontal synchronization signal HT, which determine the respective timing of the vertical scanning and horizontal scanning of the image sensor 1, for supply to the drive circuit 2. The timing control circuit 3 also generates the frame shift timing signal FT at a period coinciding with the vertical synchronization signal VT for supply to the drive circuit 2. The timing control circuit 3 performs shutter control to discharge the information charges of the image pickup portion 1i during the vertical scanning period corresponding to the amount of information charges generated at the image pickup portion 1i in order to maintain an optimum light exposure state of the image sensor 1. In other words, when the timing of the shutter operation is made faster, the period lengthens from the start of accumulation of the information charges until the start of frame transfer, and the accumulation of information charges is performed for a longer period at image pickup portion 1i. Conversely, when the timing of the shutter operation is made slower, the period shortens from the start of accumulation of the information charges until the start of frame transfer, and the accumulation of information charges is performed for a short period at image pickup portion 1i. The shutter operation for discharging the information charges of the image pickup portion 1i is accomplished through the action of a drive clock, which is supplied from the drive circuit 2 to the image sensor 1.
The sample-and-hold circuit 4 generates the image signal Y1(t) for maintaining signal levels by sampling the image signal Y0(t) in response to the sampling clock xcfx86s supplied from the sampling clock generator portion 2s. Normally, since charging and discharging of the capacitance in the output section 1d repeat according to reset clock xcfx86r, a reset level and a signal level, which corresponds to the information charge amount, alternately repeat in the image signal Y0(t) that is obtained from the output section 1d. The phase of the sampling clock xcfx86s is set so that only the signal level is extracted within the image signal Y0(t). Therefore, the image signal Y1(t), in which only the signal levels corresponding to the information charge amounts stored in output section 1d follow in succession, can be obtained.
A divider circuit 5 divides the reset clock xcfx86r and sampling clock xcfx86s as necessary so that information charges for multiple pixels can be mixed at the output section 1d by setting the reset operation of the output section 1d to be intermittent. As shown in FIG. 3, the divider circuit 5 may be composed, for example, so as to divide by two the reset clock xcfx86r and sampling clock xcfx86s that are generated in the same period as the horizontal clock xcfx86h, and supply a reset clock xcfx86r 0 and a sampling clock xcfx86s0, which have twice the period of the horizontal clock xcfx86h, to the output section 1d and the sample-and-hold circuit 4. Due to the reset clock xcfx86r1 having a doubled period, the resetting of information charges every time the information charges for two pixels accumulate in the image pickup portion 1i results in the output of the image signal Y0(t), in which levels are changed in two steps at a timing following the horizontal clock xcfx86h, from the output section 1d. 
The period in which the image pickup portion 1i of the image sensor 1 accumulates the information charges for a single image plane has a maximum length of one vertical scanning period. If the image of a dark object is captured by the sensor 1, a sufficient amount of information charges may not be obtainable, even when the accumulation period is set to the maximum length. If a sufficient amount of information charges is not obtained in the pixels of the image pickup portion 1i, the S/N ratio is susceptible to degradation during the process of conversion from charge amounts to voltage values at the output section 1d. In this sort of instance, the divider circuit 5 is operated to decrease the frequency of the reset operation of information charges at the output section 1d by xc2xd (or ⅓ or less) so that the information charges for two pixels (or for three or more pixels) are discharged together from the capacitance. Therefore, the conversion from charge amounts to voltage values is performed in a state where a sufficient amount of information charges is stored in the capacitance so that degradation of the S/N ratio can be prevented at the output section 1d of the image sensor 1.
If the information charges from a plurality of pixels are summed and extracted at the output section 1d of the image sensor 1, the amount of information extracted from the image sensor 1 decreases according to the number of pixels that are summed. For example, if information charges for two pixels are summed and the output is extracted in the output section 1d of the image sensor 1, the information amount of each line forming the object image decreases by one half. Therefore, degradation of picture quality of the reproduced image is inevitable.
Another problem accompanying the summing and outputting of information charges is introduced with the use of color filters. When performing color image capture with the image pickup apparatus, a color filter in which each pixel corresponds to a predetermined color component is commonly attached to the image pickup portion 1i of the image sensor 1. In this color filter, three primary color components or their complement color components are assigned systematically in a predetermined order to segments corresponding to each pixel. For example, in a mosaic filter, white (W) and green (G) are alternately assigned to odd-numbered line segments and cyan (Cy) and yellow (Ye) are alternately assigned to even-numbered line segments.
If the above-mentioned color filter is attached to the image pickup portion 1i of the image sensor 1, two adjacent pixels in the horizontal direction are assigned to different color components so that the information charges that accumulate in the adjacent pixels represent different colors. Thus, when the information charges of the two pixels are summed at the output section to yield image signal Y0(t), different color components mix so that is often impossible to correctly reproduce the desired color components in subsequent signal processing operations. For example, if W and G are mixed in the odd-numbered lines and Cy and Ye are mixed in the even-numbered lines, the result is W+G=Cy+Ye=R+2G+B (W=R+G+B, Cy=G+B, Ye=R+G), and the color information included in the image signal Y0(t) is of one type. Therefore, even when the pixels of the image pickup portion 1i have been made to correspond respectively to specific color components, the information corresponding to the color components cannot be reproduced from the image signal Y0(t).
It is an object of the present invention to efficiently read the information charges from the image sensor without lowering the resolution of the reproduced image even when the brightness of the object is insufficient, as well as to sum and extract the information charges of a plurality of pixels even for image sensors to which a color filter has been attached.
In one form, the present invention comprises an image sensor, in which a plurality of pixels arranged in the form of a matrix connect in every column to a plurality of vertical transfer sections and outputs of the plurality of vertical transfer sections connect to respective bits of a horizontal transfer section, for converting an output charge amount of the horizontal transfer section into a voltage value to be output at an output section; a drive circuit for transferring information charges that are generated at the plurality of pixels to the plurality of vertical transfer sections, then from the plurality of vertical transfer sections to the horizontal transfer section for every horizontal line, and further from the horizontal transfer section to the output section, and for discharging the information charges that accumulate in the output section in synchronization with the transfer operation of the horizontal transfer section; and a detector circuit for extracting in synchronization with the discharge operation of the drive circuit the voltage value that is output from the output section.
The drive circuit sets a period for the discharge operation of the output section to an integral multiple of the period of the transfer operation of the horizontal transfer section to accumulate in the output section the information charges for a plurality of pixels, and the detector circuit extracts in step fashion a change in potential during the process where information charges of a plurality of pixels sequentially accumulate at the output section in synchronization with the transfer operation of the horizontal transfer section.
According to another aspect the present invention, in the process where the information charges of a plurality of pixels accumulate in a step fashion in the output section of the image sensor, the output voltages at the steps are respectively extracted so that the voltage values corresponding to the information charge amounts of the various pixels can be obtained from the differences in output voltages of each step. Therefore, the output voltage values equivalent to the total of the information charges of the plurality of pixels can be obtained at the output section of the image sensor, and at the same time the information corresponding to the individual pixels can be obtained. Furthermore, even if different color components are mixed at the output step of the image sensor, these color components can easily be separated through signal processing operations.
Furthermore, in the present invention, when each pixel of the image sensor is mapped to the same color component for every other column, the drive circuit alternately transfers information charges to the horizontal transfer section with the odd-numbered columns and even-numbered columns of the vertical transfer section.
Therefore, in the present invention, when each pixel of the image sensor is mapped to the same color component for every other line, performing transfers for every other line from the vertical transfer section to the horizontal transfer section results in information charges that are mapped to the same color component being transferred simultaneously. Information charges for multiple pixels mapped to the same color component accumulate at the output side of the horizontal transfer section, and the voltage values corresponding to the information charge amounts are output. Simultaneously, the output voltage values at each step in the process where the information charges of multiple pixels accumulate in sequence are extracted. The information charges of multiple pixels are summed without mixing the different color components, and at the same time the summed output of multiple pixels and the individual output of each pixel can be respectively extracted.